1. Field of the Invention
The present invention relates to substrates and fabrication methods thereof, and more particularly, to a semiconductor substrate and a fabrication method thereof.
2. Description of Related Art
Flip-chip technologies facilitate to reduce chip packaging sizes and shorten signal transmission paths and therefore have been widely used for chip packaging. Various types of packages such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip module (MCM) packages can be achieved through flip-chip technologies.
In a flip-chip packaging process, a big CTE (Coefficient of Thermal Expansion) mismatch between a chip and a packaging substrate adversely affects the formation of joints between conductive bumps of the chip and contacts of the packaging substrate, thus easily resulting in delamination of the conductive bumps from the packaging substrate. On the other hand, along with increased integration of integrated circuits, a CTE mismatch between a chip and a packaging substrate induces more thermal stresses and leads to more serious warpage, thereby reducing the product reliability and resulting in failure of a reliability test.
Accordingly, an interposer made of a semiconductor material close to a semiconductor chip has been developed to overcome the above-described drawbacks caused by a CTE mismatch.
FIG. 1 is a schematic cross-sectional view showing a conventional package structure having a silicon interposer. Such a package structure not only overcomes the above-described drawbacks, but also has a reduced layout area.
For example, a packaging substrate generally has a minimum line width/pitch of 12/12 um. When the I/O count of a semiconductor chip increases, since the line width/pitch of the packaging substrate cannot be reduced, the area of the packaging substrate must be increased such that more circuits can be formed on the packaging substrate and electrically connected to the semiconductor chip having high I/O count. On the other hand, referring to FIG. 1, a plurality of semiconductor chips 11 are disposed on a silicon interposer 12 having through silicon vias (TSVs) and the silicon interposer 12 is further disposed on a packaging substrate 13. As such, the semiconductor chips 11 are electrically connected to the packaging substrate 13 through the silicon interposer 12. Through a semiconductor process, the silicon interposer 12 can have a line width/pitch of 3/3 um or less. Therefore, the semiconductor chips 11 having high I/O counts can be disposed on the through silicon interposer 2 without the need to increase the area of the packaging substrate 13. Further, the fine line width/pitch of the through silicon interposer 12 facilitates to shorten the electrical transmission path. Therefore, compared with semiconductor chips directly disposed on a packaging substrate, the semiconductor chips 11 disposed on the silicon interposer 12 can achieve a higher electrical transmission speed (efficiency).
However, when fine circuits are formed on either the side of the silicon interposer facing the semiconductor chip or the other side of the silicon interposer facing the packaging substrate through a semiconductor process, the fine circuits easily delaminate from a dielectric layer, thereby reducing the reliability of the silicon interposer.
Accordingly, a self-aligned dual damascene process is developed, which is shown in FIGS. 2A to 2I.
Referring to FIG. 2A, a first dielectric layer 21 is formed on a substrate body 20 and an etch stop layer 22 is formed on the first dielectric layer 21.
Referring to FIG. 2B, a first resist layer 23 is formed on the etch stop layer 22 and patterned to expose portions of the etch stop layer 22.
Referring to FIG. 2C, the exposed portions of the etch stop layer 22 and the first dielectric layer 21 under the exposed portions of the etch stop layer 22 are removed to form a plurality of first openings 24. Then, the first resist layer 23 is removed.
Referring to FIG. 2D, a second dielectric layer 25 is formed on the etch stop layer 22 and filled in the first openings 24.
Referring to FIG. 2E, a second resist layer 26 is formed on the second dielectric layer 25 and patterned to expose portions of the second dielectric layer 25.
Referring to FIG. 2F, the exposed portions of the second dielectric layer 25 and the etch stop layer 22 under the exposed portions of the second dielectric layer 25 are removed by etching to form second openings 27. The first openings 24 are further etched to form vias 210 that expose portions of the substrate body 20 and communicate with the second openings 27.
Referring to FIG. 2G, the second resist layer 26 is removed.
Referring to FIG. 2H, a metal layer 28 is formed in the vias 210 and the second openings 27 and on a top surface of the second dielectric layer 25 by electroplating.
Referring to FIG. 2I, the metal layer 28 on the top surface of the second dielectric layer 25 is removed by grinding. As such, the metal layer 28 in the second openings 27 constitutes a circuit layer 282 and the metal layer 28 in the vias 210 constitutes conductive vias 281 for electrically connecting the circuit layer 282 and the substrate body 20.
Therefore, by embedding the circuit layer in the dielectric layer, the self-aligned dual damascene process can prevent circuit delamination and fabricate ultra-fine circuits. However, the process needs to deposit an etch stop layer between the first dielectric layer and the second dielectric layer so as to achieve self-aligned etching through a high etch rate difference between the etch stop layer and the first or second dielectric layer. The etch stop layer made of such as silicon nitride generally has a high dielectric constant, which induces a large capacitance effect, such as an RC delay. The thicker the etch stop layer, the larger the capacitance effect and the lower the electrical signal transmission speed.
Therefore, how to overcome the above-described drawbacks has become critical.